1. Technical Field
The present invention relates to printed circuit boards (PCBs) and package substrates, and more particularly to the reduction of jitter in a semiconductor device by controlling stackup.
2. Related Art
Programmable logic devices (PLDs) are a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, programmable input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc. of San Jose, Calif. 95124. A FPGA typically includes an array of CLBs surrounded by a ring of IOBs. The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration data may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, or the like, though a computer may also be used to provide the data. The collective states of the individual memory cells then determine the function of the FPGA. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.” The FPGA is attached to a printed circuit board (PCB) of a computer or other similar device.
Another type of PLD is the complex programmable logic device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure. For purposes of clarity, FPGAs are described below though other types of PLDs and semiconductor devices may be used.
FIG. 1 shows an example printed circuit board (PCB) 100 having mounted thereon an example FPGA chip 105. A plurality of contact members, for example metal pad regions or pogo pins (not shown), extend from the upper surface of PCB 100. The FPGA chip 105 has mounted thereon a plurality of solder balls 110 for electrically connecting to the contact members of the PCB 100. The FPGA chip 105 also includes die 115 electrically connected to a carrier via bumps 120. PCB 100 includes layers for power supply voltage rails, ground and signal lines (not shown). Vias connect these layers through solder balls 110 to and through the circuitry of the FPGA 105.
PCBs can contribute to jitter in FPGAs resulting from connections to the PCB layers while the PCB voltage supply drives circuitry of the FPGA. One factor contributing to jitter is local voltage supply noise in the PCB. Parasitic inductive, capacitive, and resistive loads along the lines supplying power and signals to elements in the FPGA can cause voltage fluctuations, including ground bounce and supply bounce, which increases local power supply noise in the PCB. This noise provided to delay elements creates jitter in the FPGA on a clock signal containing the delay elements.
FIG. 2 shows a current example stackup for a twenty-four-layer PCB. This PCB 100 has three power supply planes 11, 13 and 14 and ten signal planes 1, 3, 5, 7, 9, 16, 18, 20, 22 and 24. This implementation places all the power supply planes 11, 13, and 14 in the middle of the board, without any particular rules assigned as to what order each power supply plane appears within the stackup. For example, the power supply planes can be differentiated due to their different voltages. As another example, some “core” power supply planes power timing-critical circuitry within the FPGA, whereas other power supply planes power input/output circuitry within the FPGA. Further, this stackup has two power supply planes 13 and 14 that are adjacent to each other, which allows noise from one plane to couple onto the other.
FIG. 3 shows a current example stackup for an eight-layer package substrate 300. The package substrate 300 is a PCB-like structure used to mount a silicon die. A die 315 is electrically connected to the package substrate 300 through conductive balls 320. Of note, the primary core supply, shown as “Vcc—Primary Core Supply Plane” on plane 6, and secondary core supply, shown as “Vcc—Secondary Core Supply Plane” on plane 7, are farther away from die 315 than the I/O power supply, shown as “Vcc—I/O Supply Plane on plane 4.”
FIG. 4 shows a current example stackup for a ten-layer package substrate 300. Of note, the primary core power supply, shown as “Vcc—Primary Core Supply Plane” on plane 6 is farther away from die 315 than the first I/O power supply, shown as “Vcc—I/O Supply Plane” on plane 4. Similarly, the secondary core power supply, shown as “Vcc—Secondary Core Supply Plane” on plane 10, is farther away from the die 315 than both the first and second I/O power supply planes, shown as “Vcc—I/O Supply Plane” on planes 4 and 8.
It is desirable to reduce the amount of jitter on a clock as it propagates through a PCB to and through a silicon device, such as a FPGA.